Call for Papers
The selected authors are requested to submit IEEE copyright form by March 15, 2013.
ID and password is required for submission. In case that you lost ID and password, please send your request to iitc@epapers.org
Guideline for Oral Presentation
Guideline for Poster Presentation
Call for Papers(English)
Call for Papers(Japanese)
IITC 2013 Paper Submission
The 16th annual IEEE International Interconnect Technology Conference (IITC) and exhibition, sponsored by IEEE Electron Devices Society and technically co-sponsored by the Japan Society of Applied Physics (JSAP), has announced a Call for Papers for work describing innovative developments in the critically important field of interconnections for electronic systems. The conference seeks papers on all aspects of interconnects for device, circuit board and system-level applications. The deadline for submission of paper abstracts is now extended until 5pm, January 28, 2013 (PST).
IITC 2013 will be held June 13-15 in Kyoto, Japan. It will be held adjacent to the IEEE VLSI Symposium, which is also being held in Kyoto. The conference attracts professionals from industry, academia, and national laboratories in semiconductor processing, interconnect design, and equipment development.
The conference topics include both fundamental and applied research, as well as issues related to introduction into manufacturing. Subjects of interest include all aspects of Interconnects: Materials and Unit Processes, Process Integration, Characterization, Reliability, Chip-Package Interaction (CPI), 3D Integration and TSV Technology, Novel Systems and Packaging, Novel Materials and Concepts, Back- End Memories, beyond CMOS, and MEMS as well as the Specific Interest Areas listed below.
This year, the Organizing Committee is explicitly soliciting contributions in the following specific interest areas: optical interconnects, technology-design interactions, patterning, beyond copper-low k interconnects, back-end embedded memories, and 3D integration.
CONFERENCE FORMAT:
Technical Papers: Submissions addressing all aspects of interconnect technology will be rigorously reviewed.
- Regular papers, with 3-page abstracts, will be selected for either oral or poster presentation. For accepted papers, these 3-page abstracts will be published in the IEEE conference proceedings without the opportunity for further change.
- Papers with 2-page abstracts, e.g., from Young Engineers and Students, will undergo the same review process but will be accepted only for poster presentation. Also, the 2-page abstracts will be published in the IEEE conference proceedings.
- Oral presentations will be 20 minutes in length followed by a 5-minute time slot for questions. Poster authors are requested to be at their presentations for a 2-hour period on the day of their poster display.
Exhibits/Seminars: New products, processes, analytical methods and materials will be exhibited at the conference. Supplier seminars will be held on the 1st or 2nd evenings of the conference.
SUBMISSION OF PAPERS:
Deadline: January 14, 2013
NOTE: Submission of an abstract for review and subsequent acceptance is considered by the committee as an agreement that the work will not be placed in the public domain by the author prior to the conference. Accepted papers or significant portions of the work may not be placed in the public domain prior to the conference. Violation will be grounds for automatic withdrawal of the paper by the conference committee. Inclusion of materials from publications by other authors may be done only with their expressed permission and with a citation associated with the reproduced material. Appropriate company or government clearance must be obtained by the authors before submission and an IEEE Copyright Form will be required.
Papers must be submitted electronically (Submit Paper). Please read the paper preparation and submission guidelines before preparing your paper.
ACCEPTED PAPERS WILL BE PRINTED IN THE PROCEEDINGS WITHOUT THE OPPORTUNITY FOR FURTHER CHANGE. Paper length inclusive of all illustrations, charts and tables must be 3 pages for regular oral/poster sessions and 2 pages for special poster sessions for New Engineers and Students, respectively. Contact information for each author must be listed on the first page of the paper: name, affiliation, city, state or country. Authors of accepted papers will be notified by March 8, 2013.
2013 SUBJECTS OF INTEREST and PRELIMINARY SESSION TITLES:
IITC New Directions -- Contributions in these areas strongly encouraged - Networks-on-Chip, Circuits for High-Speed and Low-Power Signaling, Fine Grain 3D with TSV sizes smaller than 200nm, Contacts and Local Interconnects, Interconnects for Biological Applications.
Materials and Unit Processes
- Dielectric materials (low k, ARC, Cap, ESL, etc.) and associated deposition processes (vapor deposition, spin-on, etc.)
- Metallization processes/equipment (PVD, CVD, ALD, Electroplating, etc.)
- Planarization processes for dielectrics and metals, equipment and metrology issues. Alternative planarization techniques
- Interconnect specific patterning processes (lithography, etch, etc.) including wet/dry strip and cleaning
- Novel or improved tools for metrology and characterization applicable to interconnect
- Unit process control and modeling
- Contacts and Local Interconnects
Process Integration for Logic or Memory
- Multilevel interconnect processes, clustered processes, novel interconnect structures, contact/via integration, metal barrier and materials interface issues, etc.
- Integration processes and issues specific to logic or memory
- Across generation manufacturing science
Characterization
- Low k dielectric porosity, etch damage, mechanical properties
- Cu grain size and orientation, resistivity, voids
- Stress and failure in 3D and SPI structures
Reliability
- Metal electromigration and stress voiding
- Dielectric integrity and mechanical stability, thermal effects, passivation issues
- Interconnect reliability prediction/modeling
- Chip-package interaction
Novel Circuits and Systems for Signaling Networks-on-Chip
- Circuits for High-Speed and Low-Power Electrical Interconnects (both on-chip and off-chip)
- New device architectures: Multi-core Technology - impact on packaging and interconnect scaling
- Interconnect performance modeling and high frequency characterization of interconnect system integration
- Advanced interconnect concepts (optical: superconductors; RF; interconnects from CPU to system components, etc.)
- RF and high frequency passive components
- Interconnects for Biological Applications
3D Integration and TSV
- Materials
- 3D Design and Modeling
- TSV etching, barrier deposiiton, electroplating processes
- Wafer bonding schemes
- Process integration
- Reliability issues
- Applications
- Fine-grained 3D, with TSV sizes smaller than 200nm
Back-End Memories and MEMS
- Materials, devices and circuits for resistance change memories (RRAM, Phase Change Memory, Conductive-Bridge RAM, MRAM, etc.)
- 3D stacked resistance change memories
- 3D stacked NAND flash memories
- MEMS devices stacked in BEOL or using sub-400C processes
Packaging
- Thermal management technology
- Green technology (SN-based solder, cu-pillar, etc.)
- Flip-chip, wafer level packaging, chip-on-chip, MCM, etc.
- Novel board level interconnect, package architectures
- interconnect structures for strengthening low-k/CU film stacks
- Seal ring and bond-bump pad design
Novel Materials and Concepts
- Advanced interconnect concepts, options and issues for post Si CMOS devices
- Emerging interconnect materials; critical materials issues and parameters for implementation (e.g. Carbon, Technology, nanowires; Nano-materials)
- Interface connections (Si-Si; Organic-Organic; Hybrid)
- Interconnects for novel non-volatile, embedded memories (PCM, resistive, etc.)
- Interconnects for display, PV and flexible devices
- Interconnects for optical applications
The submission of the abstract will be available from the end of November, 2012.
GENERAL INFORMATION:
For additional information, including Author's Kits, Supplier/Exhibit Information, Registration/Hotel Information, please contact:
IITC
c/o Semiconductor Portal, Inc.
ATT East 17F
2-17-22 Akasaka, Minato-ku, Tokyo 107-0052 Japan
Tel: +81-3-3560-3565 Fax: +81-3-3560-3566
Email: iitc_2013@semiconportal.com
